8 Bit ALU design Using Verilog
8bit ALU
Arithmetic Logic Unit performs 8 bit Arithmetic and Logic Operations.
`timescale 1ns / 1ps
module ALU_8bit(a,b,opcode,result);input [3:0]a,b;
input[2:0]opcode;
output [7:0]result;
reg [7:0]result; //the result is left-hand side of target and is declared as type reg
parameter add_op =3'b000, //addticn
sub_op =3'b001, //subtraction
mul_op =3'b010, //multiplication
and_op =3'b011, //multiplying using and gate
or_op =3'b100,// addition using or gate
not_op =3'b101, //not gate
xor_op =3'b110, //xor gate
xnor_op =3'b111; //xnor gate
always @(a or b or opcode)
begin
case(opcode)
add_op :result = a+b;
sub_op :result = a-b;
mul_op :result = a*b;
and_op :result = a&b;
or_op :result = a|b;
not_op :result = ~a; //also be ~b
xor_op :result = a^b;
xnor_op :result = ~(a^b);
endcase
end
endmodule
Test bench code:
`timescale 1ns / 1ps
module ALU_tb();
// Inputs
reg [3:0] a;
reg [3:0] b;
reg [2:0] opcode;
// Outputs
wire [7:0] result;
// Instantiate the Unit Under Test (UUT)
ALU_8bit uut (
.a(a),
.b(b),
.opcode(opcode),
.result(result)
);
initial //apply input vectors
begin
//add operation 1 + 2 and 6 + 6
#0 a = 4'b0001; b = 4'b0010; opcode = 3'b000;
#10 a = 4'b0110; b = 4'b0110; opcode = 3'b000;
//subtract operation 12 - 3 and 13 - 10
#10 a = 4'b1100; b = 4'b0011; opcode = 3'b001;
#10 a = 4'b1101; b = 4'b1010; opcode = 3'b001;
//multiply operation 12 x 7 and 15 x 3
#10 a = 4'b1100; b = 4'b0111; opcode = 3'b010;
#10 a = 4'b1111; b = 4'b0011; opcode = 3'b010;
//AND operation
#10 a = 4'b1100; b = 4'b0111; opcode = 3'b011;
#10 a = 4'b1101; b = 4'b1011; opcode = 3'b011;
//OR operation
#10 a = 4'b0101; b = 4'b1011; opcode = 3'b100;
#10 a = 4'b1001; b = 4'b1010; opcode = 3'b100;
//NOT operation
#10 a = 4'b1001; opcode = 3'b101;
#10 a = 4'b0011; opcode = 3'b101;
//exclusive-OR operation
#10 a = 4'b0111; b = 4'b1011; opcode = 3'b110;
#10 a = 4'b1010; b = 4'b0101; opcode = 3'b110;
//exclusive-NOR operation
#10 a = 4'b0110; b = 4'b0110; opcode = 3'b111;
#10 a = 4'b0011; b = 4'b1110; opcode = 3'b111;
end
initial
begin
$monitor(" A=%b | B=%b | Opcode = %b | Result=%b",a,b,opcode,result);
#300 $finish;
end
endmodule
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