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Elevator Control System using Verilog Verilog: `timescale 1ns / 1ps module LiftC(clk,reset,req_floor,stop,door,Up,Down,y); input clk,reset; input [6:0] req_floor; output reg[1:0] door; output reg[1:0] Up; output reg[1:0] Down; output reg[1:0] stop; output [6:0] y; reg [6:0] cf ; always @ (posedge clk) begin if(reset) begin cf=6'd0; stop=6'd1; door = 1'd1; Up=1'd0; Down=1'd0; end else begin if(req_floor < 6'd61) begin if(req_floor < cf ) begin cf=cf-1; door=1'd0; stop=6'd0; Up=1'd0; Down=1'd1; end else if (req_floor > cf) begin cf = cf+1; door=1'd0; stop=6'd0; Up=1'd1; Down=1'd0; end else if(req_floor == cf ) begin cf = req_floor; door=1'd1; stop=6'd1; Up=1'd0; Down=1'd0; end end end end assign y = cf; endmodule Test bench: `timescale 1ns / 1ps module LiftC_Tb(); reg clk,reset; reg [6:0] req_floor; wire [1:0] stop,door,Up,Down;  wire [6:0] y; LiftC dut(clk,reset,req_floor,stop,door,Up,Down,y); initial begin...

MIPS-Singe-Cycle-Processor MIPS (Microprocessor without Interlocked Pipelined Stages) is a family of reduced instruction set computer (RISC) instruction set architectures (ISA). QuestaSim simulation environment to simulate the operation of the designed device and VIVADO for evaluating the RTL and the Synthesis design. Supported instructions: ADD SUB SLT MUL J BEQ ADDI LW SW ALU ( arithmetic and Logic unit) code module ALU (         input [31:0] readData1, // First operand from register file     input [31:0] readData2, // Second operand from register file     input [31:0] extended, // Extended immediate value     input [2:0] ALUControl, // ALU control signal     input ALUSrc, // ALU source selector     output reg [31:0] ALU_RESULT, // ALU result     output reg Zero // Zero flag );     reg [31:0] B; // ALU second operand     // ALU operation...

Booth's multiplier Verilog code: module half_adder(input a, b, output s0, c0);   assign s0 = a ^ b;   assign c0 = a & b; endmodule module full_adder(input a, b, cin, output s0, c0);   assign s0 = a ^ b ^ cin;   assign c0 = (a & b) | (b & cin) | (a & cin); endmodule module array_multiplier(input [3:0] A, B, output [7:0] z);   reg signed p[4][4];   wire [10:0] c; // c represents carry of HA/FA   wire [5:0] s; // s represents sum of HA/FA   // For ease and readability, two diffent name s and c are used instead of single wire name.   genvar g;   generate     for(g = 0; g<4; g++) begin       and a0(p[g][0], A[g], B[0]);       and a1(p[g][1], A[g], B[1]);       and a2(p[g][2], A[g], B[2]);       and a3(p[g][3], A[g], B[3]);     end   endgenerate   assign z[0] = p[0][0];   //row 0   half_adder h0(p[0][1], p[1][0], z[1], c[0]);...

Parity Generator: Parity Generator designed is Odd Parity Generator circuit, it maintains the binary data in an odd number of 1’s, for example, the data taken is in even number of 1’s, this odd parity generator is going to maintain the data as an odd number of 1’s by adding the extra 1 to the even number of 1’s. This is the combinational circuit whose output is always dependent upon the given input data `timescale 1ns / 1ps module par_gen(x,y,z,result); input x,y,z; output result; xor (result,x,y,z);   endmodule  Test bench code: `timescale 1ns / 1ps module par_gen_tb;         // Inputs         reg x;         reg y;         reg z;         // Outputs         wire result;         // Instantiate the Unit Under Test (UUT)         par_gen uut (                 .x(x),    ...

N bit comparator:  A magnitude digital Comparator is a combinational circuit that compares two digital or binary numbers in order to find out whether one binary number is equal, less than, orgreater than the other binary number. `timescale 1ns / 1ps module comparator_nbit(a,b,Lesser,Greater,Equal); parameter n=32; input [n-1:0]a,b; output Lesser,Greater,Equal; reg Lesser=0,Greater=0,Equal=0; always @ (a,b) begin if(a>b) begin Lesser=0;Equal=0;Greater=1; end else if (a<b) begin Lesser=1;Equal=0;Greater=0; end else begin Lesser=0;Equal=1;Greater=0; end end endmodule Test bench code: `timescale 1ns / 1ps module comparator_nbit_tb;         // Inputs         reg [31:0] a;         reg [31:0] b;         // Outputs         wire Lesser;         wire Greater;         wire Equal;         // Instantiate the Unit Under Test (UUT) ...

4-Bit Carry Look Ahead Adder: A carry look-ahead adder reduces the propagation delay by introducing more complex hardware //structural for four-bit carry lookahead adder using //built-in primitives and conditional assignment module cla_4bit (a, b, cin, sum, cout); input [3:0] a, b; //define inputs and outputs input cin; output [3:0] sum; output cout; //design the logic for the generate functions and (g0, a[0], b[0]), (g1, a[1], b[1]), (g2, a[2], b[2]), (g3, a[3], b[3]); //design the logic for the propagate functions xor (p0, a[0], b[0]), (p1, a[1], b[1]), (p2, a[2], b[2]), (p3, a[3], b[3]); //design the logic for the sum equations xor (sum[0], p0, cin), (sum[1], p1, c0), (sum[2], p2, c1), (sum[3], p3, c2);//design the logic for the carry equations //using the continuous assign statement assign c0 = g0 | (p0 & cin), c1 = g1 | (p1 & g0) | (p1 & p0 & cin), c2 = g2 | (p2 & g1) | (p2 & p1 & g0)  | (p2 & p1 & p0 & cin), c3 = g3 | (p3 & g2) | (p...

4bit synchronous BCD  counter:  A BCD(binary coded decimal)counter is one of the 4-bit binary counters, which counts from 0 to a pre-determined count with an applied clock signal. When the count reaches the predetermined count value, it resets all the flip-flops and starts to count again from 0. This type of counter is designed by using 4 JK flip flops and counts from 0 to 9, and the result is represented in digital form. After reaching the count of 9 (1001), it Verilog code: resets and starts again module bcd_counter(input clock, clear,            output reg [3:0] count); reg [3:0] t; always @ (posedge clock) begin   if (clear)    begin     t <= 4'b0000;     count <= 4'b0000;   end   else    begin     t <= t + 1;     if (t == 4'b1001)      begin       t <= 4'b0000;     end     count <= t;   end end endmo...

A Johnson counter is a digital circuit with a series of flip flops connected in a feedback manner. The circuit is a special type of shift register where the last flip flop's complement output is fed back to the first flip flop's input. This is almost similar to the ring counter with a few extra advantages. The Johnson counter's main advantage is that it only needs half the number of flip-flops compared to the standard ring counter, and then it's modulo number is halved. So an n-stage Johnson counter will circulate a single data bit, giving a sequence of 2n different states and can therefore be considered a mod-2n counter. Verilog code:  module johnson_counter(clk,reset,count);   //Johnson counter can be implement for any number of bits by changing Width Parameter.Initially it was 4. parameter WIDTH=4;   //inputs input clk,reset;   //outputs output reg [WIDTH-1:0] count; always@(posedge clk) begin if(reset) count={~count[0],count[WIDTH-1:1]}; else  count=1; end ...

Verilog code for clock divider:  A clock divider circuit creates lower frequency clock signals from an input clock source. The divider circuit counts input clock cycles, and drives the output clock low and then high for some number of input clock cycles. `timescale 1ns/1ps; module clockdivider(clk,divideby2,divideby4,divideby8,rst); input clk,rst; reg [3:0]count; output reg divideby2,divideby4,divideby8,divideby16; always@(posedge clk) begin if(rst==0) count=4'b0000; else count=count+1;   divideby2=count[0];   divideby4=count[1];   divideby8=count[2];   divideby16=count[3]; end endmodule Test bench code: `timescale 1ns/1ps; module clockdivider_tb;         // Inputs         reg clk;         reg rst;         // Outputs         wire divideby2;         wire divideby4;         wire divideby8;         wire divi...