clock divider using Verilog

Verilog code for clock divider: 

A clock divider circuit creates lower frequency clock signals from an input clock source. The divider circuit counts input clock cycles, and drives the output clock low and then high for some number of input clock cycles.

`timescale 1ns/1ps;

module clockdivider(clk,divideby2,divideby4,divideby8,rst);

input clk,rst;

reg [3:0]count;

output reg divideby2,divideby4,divideby8,divideby16;

always@(posedge clk)

begin

if(rst==0)

count=4'b0000;

else

count=count+1;

  divideby2=count[0];

  divideby4=count[1];

  divideby8=count[2];

  divideby16=count[3];

end

endmodule

Test bench code:

`timescale 1ns/1ps;

module clockdivider_tb;

        // Inputs

        reg clk;

        reg rst;

        // Outputs

        wire divideby2;

        wire divideby4;

        wire divideby8;

        wire divideby16;

        // Instantiate the Unit Under Test (UUT)

        clockdivider uut (

                .clk(clk), 

                .divideby2(divideby2), 

                .divideby4(divideby4), 

                .divideby8(divideby8), 

                .divideby16(divideby16),

                .rst(rst)

        );

        initial begin

                // Initialize Inputs

                clk = 0;

                rst = 0;

                #50 rst=1;

                // Add stimulus here

        end

        always

        #10 clk=~clk;

        initial 

        #100 $finish;

endmodule

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