Parity Generator using Verilog

Parity Generator:

Parity Generator designed is Odd Parity Generator circuit, it maintains the binary data in an odd number of 1’s, for example, the data taken is in even number of 1’s, this odd parity generator is going to maintain the data as an odd number of 1’s by adding the extra 1 to the even number of 1’s. This is the combinational circuit whose output is always dependent upon the given input data

`timescale 1ns / 1ps

module par_gen(x,y,z,result);

input x,y,z;

output result;

xor (result,x,y,z);  

endmodule 

Test bench code:

`timescale 1ns / 1ps

module par_gen_tb;

        // Inputs

        reg x;

        reg y;

        reg z;

        // Outputs

        wire result;

        // Instantiate the Unit Under Test (UUT)

        par_gen uut (

                .x(x), 

                .y(y), 

                .z(z), 

                .result(result)

        );

        initial begin

// Initialize Inputs

x = 0;

y = 0;

z = 0;

// Wait 100 ns for global reset to finish

#100;

// Add stimulus here

x = 0;

y = 0;

z = 1;

// Wait 100 ns for global reset to finish

#100;

x = 0;

y = 1;

z = 0;

// Wait 100 ns for global reset to finish

#100;

x = 0;

y = 1;

z = 1;

// Wait 100 ns for global reset to finish

#100;

x = 1;

y = 0;

z = 0;

// Wait 100 ns for global reset to finish

#100;

x = 1;

y = 0;

z = 1;

// Wait 100 ns for global reset to finish

#100;

x = 1;

y = 1;

z = 0;

// Wait 100 ns for global reset to finish

#100;

x = 1;

y = 1;

z = 1;

// Wait 100 ns for global reset to finish

#100;

end

endmodule

#verilog #rtlcoding