Ring counter

Ring counter :

A ring counter is a special type of application of the Serial IN Serial OUT Shift register. The only difference between the shift register and the ring counter is that the last flip flop outcome is taken as the output in the shift register. But in the ring counter, this outcome is passed to the first flip flop as an input. All of the remaining things in the ring counter are the same as the shift register. In the Ring counterNo. of states in Ring counter = No. of flip-flop used

Verilog code 

`timescale 1ns / 1ps

module ring_counter( clk,

     reset, count );

  parameter WIDTH=4;

  input clk,reset;

  output reg [WIDTH-1:0] count;

  always@(posedge clk)

begin

if(reset)

count={count[0],count[WIDTH-1:1]};

else 

count=4'b0001;

end

endmodule

Test bench: 

`timescale 1ns / 1ps

module ring_counter_tb;

 // Inputs

 reg clk;

 reg reset;

 parameter WIDTH=4;

 // Outputs

 wire [WIDTH-1:0] count;

 // Instantiate the Unit Under Test (UUT)

 ring_counter uut (

  .clk(clk), 

  .reset(reset), 

  .count(count)

 );

always #10 clk=~clk;

 initial begin

  // Initialize Inputs

  clk = 0;

  reset = 0;

  $monitor ("T=%0t out=%b", $time, count);

 #50 reset=1;

  // Wait 100 ns for global reset to finish

  

        

  // Add stimulus here

 end

 initial

 #300 $finish;    

endmodule

#verilog #rtlcode #ringcounter