single port RAM

Single port RAM : The Single Port RAM block models RAM that supports sequential read and write

operations. If you want to model RAM that supports simultaneous read and write

operations, use the Dual Port RAM block.

Verilog code for single port RAM 

`timescale 1ns / 1ps

module single_port_ram

#(parameter addr_width = 6,

parameter data_width = 8,

parameter depth = 64)

                (

                input [data_width-1:0] data, //this is input data

                                input [addr_width-1:0] addr, //address

                                input we,clk, //we is read and write control,high is write, low is read

                                output [data_width-1:0] q //q is outptut data

                                );

//Declare RAM variable

reg [data_width-1:0] ram [depth-1:0];

//address register

reg [addr_width-1:0] addr_reg;

always @(posedge clk)

begin

if(we) //if we=1 write data into RAM

     ram[addr] <=data; 

         else //if we=0 then read data out

             addr_reg <=addr; //gets address value from outisde of module

end

assign q= ram[addr_reg]; //read data to q

endmodule 

Text bench code for single port RAM 

`timescale 1ns / 1ps

module single_port_ram_tb;

parameter addr_width = 6;

parameter data_width = 8;

parameter depth = 64;

        // Inputs

        reg [data_width-1:0] data;

        reg [addr_width:0] addr;

        reg we;

        reg clk;

        // Outputs

        wire [data_width-1:0] q;

        // Instantiate the Unit Under Test (UUT)

        single_port_ram uut (

                .data(data), 

                .addr(addr), 

                .we(we), 

                .clk(clk), 

                .q(q)

        );

        initial begin

                // Initialize Inputs

                clk=0;

                forever #5 clk=~clk;

end

// write data into the address 0,1,2 and read it out

initial begin

data=8'h01;

addr=5'd0; //address 0

we=1'b1; //write data

#10;

data=8'h02;

addr=5'd1; //address 1

#10;

data=8'h03;

addr=5'd2; //address 1

#10;

 //read operation

addr=5'd0; //address 1

we=1'b0; //read address 0, it should be data 01

#10;

addr=5'd1; //read address 0, it should be data 02

#10;

addr=5'd2; //read address 0, it should be data 02

#10;

end

endmodule

#verilog #ece Verilog projects ECE projects