qyestverse

`timescale 1ns / 1ps module washing_machine_fsm (     input clk,     input rst_n, // Active low reset     input start,             input door_closed,       input water_level,cycle_complete,      output reg [2:0] state,      output reg motor_on,         output reg water_valve,      output reg drain_valve,      output reg buzzer        );     localparam IDLE = 3'b000;     localparam FILL_WATER = 3'b001;     localparam WASH = 3'b010;     localparam RINSE = 3'b011;     localparam SPIN = 3'b100;     localparam DRAIN_WATER = 3'b101;     localparam END = 3'b110;     localparam ERROR = 3'b111;     reg [2:0] next_state;     // State transition logic    ...

Direct mapped cache using Verilog  `timescale 1ns / 1ps module direct_mapped_cache #(     parameter DATA_WIDTH = 32, // Data width (32-bit)     parameter ADDR_WIDTH = 8, // Address width (8-bit)     parameter CACHE_SIZE = 16 // Cache size in terms of number of blocks (16 blocks) )(     input clk, // Clock signal     input rst, // Reset signal     input [ADDR_WIDTH-1:0] address, // Address from CPU     input [DATA_WIDTH-1:0] write_data, // Data to be written     input mem_write, // Memory write signal     input mem_read, // Memory read signal     output reg [DATA_WIDTH-1:0] read_data, // Data to CPU     output reg hit // Cache hit signal );     // Cache line structure     reg [DATA_WIDTH-1:0] cache_data [CACHE_SIZE-1:0]; // Cache memory for storing data     reg ...

Dual port RAM using Verilog  `timescale 1ns / 1ps module dual_port_ram       # (parameter data_width=8,               parameter addr_width=4,                         parameter depth=16                         )     ( input clk, //clock         input wr_en, //write enable for port 0         input [data_width-1:0] data_in, //Input data to port 0.         input [addr_width-1:0] addr_in_0, //address for port 0         input [addr_width-1:0] addr_in_1, //address for port 1         input port_en_0, //enable port 0.         input port_en_1, //enable port 1.         output [data_width-1:0] data_out_0, //output data from port 0.       ...

Hi welcome to qyestverse   Verilog code for vending machine: `timescale 1ns / 1ps module vending_machine (     input clk,reset,select_item,              input [1:0] coin, // Input coin: 2'b01 for 1 unit, 2'b10 for 2 units     output reg dispense,       output reg [3:0] change  );     parameter IDLE = 3'b000,               ONE_UNIT = 3'b001,               TWO_UNITS = 3'b010,               ITEM_READY = 3'b011,               DISPENSE = 3'b100;     reg [2:0] current_state, next_state;     reg [3:0] amount; // Tracks the inserted amount     always @(posedge clk or posedge reset) begin         if (reset) begin             current_state <= IDLE;      ...