cache maping using Verilog
Direct mapped cache using Verilog `timescale 1ns / 1ps module direct_mapped_cache #( parameter DATA_WIDTH = 32, // Data width (32-bit) parameter ADDR_WIDTH = 8, // Address width (8-bit) parameter CACHE_SIZE = 16 // Cache size in terms of number of blocks (16 blocks) )( input clk, // Clock signal input rst, // Reset signal input [ADDR_WIDTH-1:0] address, // Address from CPU input [DATA_WIDTH-1:0] write_data, // Data to be written input mem_write, // Memory write signal input mem_read, // Memory read signal output reg [DATA_WIDTH-1:0] read_data, // Data to CPU output reg hit // Cache hit signal ); // Cache line structure reg [DATA_WIDTH-1:0] cache_data [CACHE_SIZE-1:0]; // Cache memory for storing data reg ...
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