Conversion of number system

Number Converter

Number Converter (Supports 128-bit Numbers)

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clock divider using Verilog

Verilog code for clock divider:  A clock divider circuit creates lower frequency clock signals from an input clock source. The divider circuit counts input clock cycles, and drives the output clock low and then high for some number of input clock cycles. `timescale 1ns/1ps; module clockdivider(clk,divideby2,divideby4,divideby8,rst); input clk,rst; reg [3:0]count; output reg divideby2,divideby4,divideby8,divideby16; always@(posedge clk) begin if(rst==0) count=4'b0000; else count=count+1;   divideby2=count[0];   divideby4=count[1];   divideby8=count[2];   divideby16=count[3]; end endmodule Test bench code: `timescale 1ns/1ps; module clockdivider_tb;         // Inputs         reg clk;         reg rst;         // Outputs         wire divideby2;         wire divideby4;         wire divideby8;         wire divi...
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Booth's Multiplier

Booth's multiplier Verilog code: module half_adder(input a, b, output s0, c0);   assign s0 = a ^ b;   assign c0 = a & b; endmodule module full_adder(input a, b, cin, output s0, c0);   assign s0 = a ^ b ^ cin;   assign c0 = (a & b) | (b & cin) | (a & cin); endmodule module array_multiplier(input [3:0] A, B, output [7:0] z);   reg signed p[4][4];   wire [10:0] c; // c represents carry of HA/FA   wire [5:0] s; // s represents sum of HA/FA   // For ease and readability, two diffent name s and c are used instead of single wire name.   genvar g;   generate     for(g = 0; g<4; g++) begin       and a0(p[g][0], A[g], B[0]);       and a1(p[g][1], A[g], B[1]);       and a2(p[g][2], A[g], B[2]);       and a3(p[g][3], A[g], B[3]);     end   endgenerate   assign z[0] = p[0][0];   //row 0   half_adder h0(p[0][1], p[1][0], z[1], c[0]);...
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N bit comparator

N bit comparator:  A magnitude digital Comparator is a combinational circuit that compares two digital or binary numbers in order to find out whether one binary number is equal, less than, orgreater than the other binary number. `timescale 1ns / 1ps module comparator_nbit(a,b,Lesser,Greater,Equal); parameter n=32; input [n-1:0]a,b; output Lesser,Greater,Equal; reg Lesser=0,Greater=0,Equal=0; always @ (a,b) begin if(a>b) begin Lesser=0;Equal=0;Greater=1; end else if (a<b) begin Lesser=1;Equal=0;Greater=0; end else begin Lesser=0;Equal=1;Greater=0; end end endmodule Test bench code: `timescale 1ns / 1ps module comparator_nbit_tb;         // Inputs         reg [31:0] a;         reg [31:0] b;         // Outputs         wire Lesser;         wire Greater;         wire Equal;         // Instantiate the Unit Under Test (UUT) ...
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