qyestverse

Single port RAM : The Single Port RAM block models RAM that supports sequential read and write operations. If you want to model RAM that supports simultaneous read and write operations, use the Dual Port RAM block. Verilog code for single port RAM  `timescale 1ns / 1ps module single_port_ram #(parameter addr_width = 6, parameter data_width = 8, parameter depth = 64)                 (                 input [data_width-1:0] data, //this is input data                                 input [addr_width-1:0] addr, //address                                 input we,clk, //we is read and write control,high is write, low is read                               ...

function [ gray ] = RGBTOGRAY( RGB , option ) [H W L]=size(RGB); gray=zeros(H,W); gray=double(gray); for i=1:H     for j=1:W         if option==1         gray(i,j)=(RGB(i,j,1)+RGB(i,j,2)+RGB(i,j,3))/3;         end         if option==2         gray(i,j)=RGB(i,j,1)*0.7+RGB(i,j,2)*0.1+RGB(i,j,3)*0.2;         end         if option==3         gray(i,j)=RGB(i,j,1);         end         if option==4         gray(i,j)=RGB(i,j,2);         end         if option==5         gray(i,j)=RGB(i,j,3);         end     end end gray=uint8(gray); end RGB to Gray image conversion using MATLAB. #MATLAB #matlab ECE projects ECE MATLAB projects 

Elevator Control System using Verilog Verilog: `timescale 1ns / 1ps module LiftC(clk,reset,req_floor,stop,door,Up,Down,y); input clk,reset; input [6:0] req_floor; output reg[1:0] door; output reg[1:0] Up; output reg[1:0] Down; output reg[1:0] stop; output [6:0] y; reg [6:0] cf ; always @ (posedge clk) begin if(reset) begin cf=6'd0; stop=6'd1; door = 1'd1; Up=1'd0; Down=1'd0; end else begin if(req_floor < 6'd61) begin if(req_floor < cf ) begin cf=cf-1; door=1'd0; stop=6'd0; Up=1'd0; Down=1'd1; end else if (req_floor > cf) begin cf = cf+1; door=1'd0; stop=6'd0; Up=1'd1; Down=1'd0; end else if(req_floor == cf ) begin cf = req_floor; door=1'd1; stop=6'd1; Up=1'd0; Down=1'd0; end end end end assign y = cf; endmodule Test bench: `timescale 1ns / 1ps module LiftC_Tb(); reg clk,reset; reg [6:0] req_floor; wire [1:0] stop,door,Up,Down;  wire [6:0] y; LiftC dut(clk,reset,req_floor,stop,door,Up,Down,y); initial begin...

Vivo X200 Pro Specifications  Vivo X200 pro has a large 6.78 inch 8T LTPO 1.5K resolution display With 1800 nits HBM and also supports 120Hz refresh rate. Vivo X200 pro is powered by MediaTek Dimensity 9400 chipset ,it uses  LPDDR5x RAM and UFS 4.0 storage. The Immortalis G925 GPU( graphics processing unit).It runs on Android 15 The rear camera setup includes a 50MP Sony LYT-818 OIS+ 50MP Samsung JN1 Ultrawide+ 200MP HP9 periscope camera and features a V3+ chip.There is a 32MP front camera. It's packed with 6000mAh battery support s 90 watt charging with USB 3.2 Gen 1 port It also offers a 30 watt wireless charging Other features: WiFi 7, 6, 5,Bluetooth version 5.4, Ultrasonic small size In-display fingerprint scanner, Dual stereo speakers, IR blaster for remote control,X-axis linear motor for haptics,IP68 + IP69 rating, 8.2mm & 8.49mm thickness, 223 & 228 gram weight. #qyestverse VIVO X200 Pro #Vivo #VivoX200Pro #LYT818

MIPS-Singe-Cycle-Processor MIPS (Microprocessor without Interlocked Pipelined Stages) is a family of reduced instruction set computer (RISC) instruction set architectures (ISA). QuestaSim simulation environment to simulate the operation of the designed device and VIVADO for evaluating the RTL and the Synthesis design. Supported instructions: ADD SUB SLT MUL J BEQ ADDI LW SW ALU ( arithmetic and Logic unit) code module ALU (         input [31:0] readData1, // First operand from register file     input [31:0] readData2, // Second operand from register file     input [31:0] extended, // Extended immediate value     input [2:0] ALUControl, // ALU control signal     input ALUSrc, // ALU source selector     output reg [31:0] ALU_RESULT, // ALU result     output reg Zero // Zero flag );     reg [31:0] B; // ALU second operand     // ALU operation...

Oppo K12 Plus specifications: OPPO K12 Plus has a 6.67-inch AMOLED FHD+ display with 120Hz refresh rate , offers a 1100nits peak brightness and has 2160Hz PWM dimming. It is powered by Snapdragon 7 Gen 3 chipset. It comes with 8GB LPDDR4x RAM , 8GB virtual RAM and  128GB / 256GB UFS 3.1 storage . For  additional storage  microSD card slot via hybrid SIM slot  OPPO K12 Plus  is equipped with 6,400mAh battery and supports 80W charging.  It features a 16MP selfie camera ,Rear camera setup includes a 50MP Sony LYT-600 (OIS) + 8MP IMX355 Ultra wide. It runs in Android 14 , ColorOS 14 Other features : In-display fingerprint sensor, dual speakers, x-axis linear motor, 11,147 mm^2  graphite sheet heat dissipation. Wi-Fi 6, Bluetooth 5.3, USB-C, NFC, IR blaster, offline communication,162.5 x 75.3 x 8.37mm dimensions .192 grams ,IP54 rating Oppo K12 Plus price: - 8GB+256GB: 1,899 CNY (~Rs 22,610; ~$270)  - 12GB+256GB: 2,099 CNY (~Rs 24,990; ~$300) - 12GB+51...

Booth's multiplier Verilog code: module half_adder(input a, b, output s0, c0);   assign s0 = a ^ b;   assign c0 = a & b; endmodule module full_adder(input a, b, cin, output s0, c0);   assign s0 = a ^ b ^ cin;   assign c0 = (a & b) | (b & cin) | (a & cin); endmodule module array_multiplier(input [3:0] A, B, output [7:0] z);   reg signed p[4][4];   wire [10:0] c; // c represents carry of HA/FA   wire [5:0] s; // s represents sum of HA/FA   // For ease and readability, two diffent name s and c are used instead of single wire name.   genvar g;   generate     for(g = 0; g<4; g++) begin       and a0(p[g][0], A[g], B[0]);       and a1(p[g][1], A[g], B[1]);       and a2(p[g][2], A[g], B[2]);       and a3(p[g][3], A[g], B[3]);     end   endgenerate   assign z[0] = p[0][0];   //row 0   half_adder h0(p[0][1], p[1][0], z[1], c[0]);...