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Vivo X200 Pro Specifications  Vivo X200 pro has a large 6.78 inch 8T LTPO 1.5K resolution display With 1800 nits HBM and also supports 120Hz refresh rate. Vivo X200 pro is powered by MediaTek Dimensity 9400 chipset ,it uses  LPDDR5x RAM and UFS 4.0 storage. The Immortalis G925 GPU( graphics processing unit).It runs on Android 15 The rear camera setup includes a 50MP Sony LYT-818 OIS+ 50MP Samsung JN1 Ultrawide+ 200MP HP9 periscope camera and features a V3+ chip.There is a 32MP front camera. It's packed with 6000mAh battery support s 90 watt charging with USB 3.2 Gen 1 port It also offers a 30 watt wireless charging Other features: WiFi 7, 6, 5,Bluetooth version 5.4, Ultrasonic small size In-display fingerprint scanner, Dual stereo speakers, IR blaster for remote control,X-axis linear motor for haptics,IP68 + IP69 rating, 8.2mm & 8.49mm thickness, 223 & 228 gram weight. #qyestverse VIVO X200 Pro #Vivo #VivoX200Pro #LYT818

MIPS-Singe-Cycle-Processor MIPS (Microprocessor without Interlocked Pipelined Stages) is a family of reduced instruction set computer (RISC) instruction set architectures (ISA). QuestaSim simulation environment to simulate the operation of the designed device and VIVADO for evaluating the RTL and the Synthesis design. Supported instructions: ADD SUB SLT MUL J BEQ ADDI LW SW ALU ( arithmetic and Logic unit) code module ALU (         input [31:0] readData1, // First operand from register file     input [31:0] readData2, // Second operand from register file     input [31:0] extended, // Extended immediate value     input [2:0] ALUControl, // ALU control signal     input ALUSrc, // ALU source selector     output reg [31:0] ALU_RESULT, // ALU result     output reg Zero // Zero flag );     reg [31:0] B; // ALU second operand     // ALU operation...

Oppo K12 Plus specifications: OPPO K12 Plus has a 6.67-inch AMOLED FHD+ display with 120Hz refresh rate , offers a 1100nits peak brightness and has 2160Hz PWM dimming. It is powered by Snapdragon 7 Gen 3 chipset. It comes with 8GB LPDDR4x RAM , 8GB virtual RAM and  128GB / 256GB UFS 3.1 storage . For  additional storage  microSD card slot via hybrid SIM slot  OPPO K12 Plus  is equipped with 6,400mAh battery and supports 80W charging.  It features a 16MP selfie camera ,Rear camera setup includes a 50MP Sony LYT-600 (OIS) + 8MP IMX355 Ultra wide. It runs in Android 14 , ColorOS 14 Other features : In-display fingerprint sensor, dual speakers, x-axis linear motor, 11,147 mm^2  graphite sheet heat dissipation. Wi-Fi 6, Bluetooth 5.3, USB-C, NFC, IR blaster, offline communication,162.5 x 75.3 x 8.37mm dimensions .192 grams ,IP54 rating Oppo K12 Plus price: - 8GB+256GB: 1,899 CNY (~Rs 22,610; ~$270)  - 12GB+256GB: 2,099 CNY (~Rs 24,990; ~$300) - 12GB+51...

Booth's multiplier Verilog code: module half_adder(input a, b, output s0, c0);   assign s0 = a ^ b;   assign c0 = a & b; endmodule module full_adder(input a, b, cin, output s0, c0);   assign s0 = a ^ b ^ cin;   assign c0 = (a & b) | (b & cin) | (a & cin); endmodule module array_multiplier(input [3:0] A, B, output [7:0] z);   reg signed p[4][4];   wire [10:0] c; // c represents carry of HA/FA   wire [5:0] s; // s represents sum of HA/FA   // For ease and readability, two diffent name s and c are used instead of single wire name.   genvar g;   generate     for(g = 0; g<4; g++) begin       and a0(p[g][0], A[g], B[0]);       and a1(p[g][1], A[g], B[1]);       and a2(p[g][2], A[g], B[2]);       and a3(p[g][3], A[g], B[3]);     end   endgenerate   assign z[0] = p[0][0];   //row 0   half_adder h0(p[0][1], p[1][0], z[1], c[0]);...

8bit ALU  Arithmetic Logic Unit performs 8 bit Arithmetic and Logic Operations. `timescale 1ns / 1ps module ALU_8bit(a,b,opcode,result); input [3:0]a,b; input[2:0]opcode; output [7:0]result; reg [7:0]result; //the result is left-hand side of target and is declared as type reg parameter add_op =3'b000, //addticn sub_op =3'b001, //subtraction mul_op =3'b010, //multiplication and_op =3'b011, //multiplying using and gate or_op =3'b100,// addition using or gate not_op =3'b101, //not gate xor_op =3'b110, //xor gate xnor_op =3'b111; //xnor gate always @(a or b or opcode) begin case(opcode) add_op :result = a+b; sub_op :result = a-b; mul_op :result = a*b; and_op :result = a&b; or_op :result = a|b; not_op :result = ~a; //also be ~b xor_op :result = a^b; xnor_op :result = ~(a^b); endcase end endmodule Test bench code: `timescale 1ns / 1ps module ALU_tb(); // Inputs         reg [3:0] a;         reg [3:0] b;         reg [2:0] opc...

Honor X60 Pro specifications Honor X60 has 6.78-inch curved-AMOLED( active matrix organic light emitting diode) display ,screen with 2700 x 1224p resolution. Honor X60 is powered by Snapdragon 6 Gen 1. It is available in 4 variants of RAM/ROmM i,e 8GB+128GB | 8GB+256GB | 12GB+256GB | 12GB+512GB and 512GB variant supports SMS via satellite connectivity  It is packed with 6,600mAh battery and supports 66W charging the dimensions are 162.8 x 75.5 x 7.98mm and it weighs 188 grams Thank you for reading . #qyestverse qyestverse Honor X60 pro #Honor #HonorX60Pro #HonorX60

Spectrum analyzer using Python with the interface of ESP8266.The Designed Analyzer takes the input Time Domain signals and outputs the Frequency Domain signals with the usage of the FFT Algorithm. Aurdino code :  const int x=1024; // 2^13 int data[x]; void setup() {   Serial.begin(115200); } void loop()  {     for(int i=0;i<x;i++)     {       data[i]=analogRead(A0);     }     for(int i=0;i<x;i++)     {      Serial.println(data[i]);      }   delay(5000);   } Python code for spectrum analyser: from time import sleep from vpython import* import math as m import cmath as cm import serial import matplotlib.pyplot as plt c1=canvas(background=color.black,width=1800,height=600) class Circle:     def __init__(self,X=0,Y=0,Color=color.red,Radius=1,Rate=25):         self.circle=curve(color=Color,radius=0.02)         self.X=X...

Python code for attendance system using facial recognition: import cv2 import os import numpy as np import pandas as pd import face_recognition from tkinter import filedialog from PIL import Image from kivy.app import App from kivy.uix.camera import Camera from kivy.uix.gridlayout import GridLayout from kivy.uix.image import Image from kivy.graphics.texture import Texture from kivy.uix.button import Button from kivy.uix.spinner import Spinner from kivy.clock import Clock def enhance(img):     img = cv2.cvtColor(img, cv2.COLOR_BGR2RGB)     return img def findEncodings(images):     encodelist = []     for img in images:         img = enhance(img)         encoding = face_recognition.face_encodings(img)[0]         encodelist.append(encoding)     return encodelist def add_database(directory):     # create Codes.csv file if it doesn't exist     if not os.path.exist...

Parity Generator: Parity Generator designed is Odd Parity Generator circuit, it maintains the binary data in an odd number of 1’s, for example, the data taken is in even number of 1’s, this odd parity generator is going to maintain the data as an odd number of 1’s by adding the extra 1 to the even number of 1’s. This is the combinational circuit whose output is always dependent upon the given input data `timescale 1ns / 1ps module par_gen(x,y,z,result); input x,y,z; output result; xor (result,x,y,z);   endmodule  Test bench code: `timescale 1ns / 1ps module par_gen_tb;         // Inputs         reg x;         reg y;         reg z;         // Outputs         wire result;         // Instantiate the Unit Under Test (UUT)         par_gen uut (                 .x(x),    ...

N bit comparator:  A magnitude digital Comparator is a combinational circuit that compares two digital or binary numbers in order to find out whether one binary number is equal, less than, orgreater than the other binary number. `timescale 1ns / 1ps module comparator_nbit(a,b,Lesser,Greater,Equal); parameter n=32; input [n-1:0]a,b; output Lesser,Greater,Equal; reg Lesser=0,Greater=0,Equal=0; always @ (a,b) begin if(a>b) begin Lesser=0;Equal=0;Greater=1; end else if (a<b) begin Lesser=1;Equal=0;Greater=0; end else begin Lesser=0;Equal=1;Greater=0; end end endmodule Test bench code: `timescale 1ns / 1ps module comparator_nbit_tb;         // Inputs         reg [31:0] a;         reg [31:0] b;         // Outputs         wire Lesser;         wire Greater;         wire Equal;         // Instantiate the Unit Under Test (UUT) ...

4-Bit Carry Look Ahead Adder: A carry look-ahead adder reduces the propagation delay by introducing more complex hardware //structural for four-bit carry lookahead adder using //built-in primitives and conditional assignment module cla_4bit (a, b, cin, sum, cout); input [3:0] a, b; //define inputs and outputs input cin; output [3:0] sum; output cout; //design the logic for the generate functions and (g0, a[0], b[0]), (g1, a[1], b[1]), (g2, a[2], b[2]), (g3, a[3], b[3]); //design the logic for the propagate functions xor (p0, a[0], b[0]), (p1, a[1], b[1]), (p2, a[2], b[2]), (p3, a[3], b[3]); //design the logic for the sum equations xor (sum[0], p0, cin), (sum[1], p1, c0), (sum[2], p2, c1), (sum[3], p3, c2);//design the logic for the carry equations //using the continuous assign statement assign c0 = g0 | (p0 & cin), c1 = g1 | (p1 & g0) | (p1 & p0 & cin), c2 = g2 | (p2 & g1) | (p2 & p1 & g0)  | (p2 & p1 & p0 & cin), c3 = g3 | (p3 & g2) | (p...

4bit synchronous BCD  counter:  A BCD(binary coded decimal)counter is one of the 4-bit binary counters, which counts from 0 to a pre-determined count with an applied clock signal. When the count reaches the predetermined count value, it resets all the flip-flops and starts to count again from 0. This type of counter is designed by using 4 JK flip flops and counts from 0 to 9, and the result is represented in digital form. After reaching the count of 9 (1001), it Verilog code: resets and starts again module bcd_counter(input clock, clear,            output reg [3:0] count); reg [3:0] t; always @ (posedge clock) begin   if (clear)    begin     t <= 4'b0000;     count <= 4'b0000;   end   else    begin     t <= t + 1;     if (t == 4'b1001)      begin       t <= 4'b0000;     end     count <= t;   end end endmo...

Ring counter : A ring counter is a special type of application of the Serial IN Serial OUT Shift register. The only difference between the shift register and the ring counter is that the last flip flop outcome is taken as the output in the shift register. But in the ring counter, this outcome is passed to the first flip flop as an input. All of the remaining things in the ring counter are the same as the shift register. In the Ring counterNo. of states in Ring counter = No. of flip-flop used Verilog code  `timescale 1ns / 1ps module ring_counter( clk,      reset, count );   parameter WIDTH=4;   input clk,reset;   output reg [WIDTH-1:0] count;   always@(posedge clk) begin if(reset) count={count[0],count[WIDTH-1:1]}; else  count=4'b0001; end endmodule Test bench:  `timescale 1ns / 1ps module ring_counter_tb;  // Inputs  reg clk;  reg reset;  parameter WIDTH=4;  // Outputs  wire [WIDTH-1:0] count;  // Ins...

A Johnson counter is a digital circuit with a series of flip flops connected in a feedback manner. The circuit is a special type of shift register where the last flip flop's complement output is fed back to the first flip flop's input. This is almost similar to the ring counter with a few extra advantages. The Johnson counter's main advantage is that it only needs half the number of flip-flops compared to the standard ring counter, and then it's modulo number is halved. So an n-stage Johnson counter will circulate a single data bit, giving a sequence of 2n different states and can therefore be considered a mod-2n counter. Verilog code:  module johnson_counter(clk,reset,count);   //Johnson counter can be implement for any number of bits by changing Width Parameter.Initially it was 4. parameter WIDTH=4;   //inputs input clk,reset;   //outputs output reg [WIDTH-1:0] count; always@(posedge clk) begin if(reset) count={~count[0],count[WIDTH-1:1]}; else  count=1; end ...

Verilog code for clock divider:  A clock divider circuit creates lower frequency clock signals from an input clock source. The divider circuit counts input clock cycles, and drives the output clock low and then high for some number of input clock cycles. `timescale 1ns/1ps; module clockdivider(clk,divideby2,divideby4,divideby8,rst); input clk,rst; reg [3:0]count; output reg divideby2,divideby4,divideby8,divideby16; always@(posedge clk) begin if(rst==0) count=4'b0000; else count=count+1;   divideby2=count[0];   divideby4=count[1];   divideby8=count[2];   divideby16=count[3]; end endmodule Test bench code: `timescale 1ns/1ps; module clockdivider_tb;         // Inputs         reg clk;         reg rst;         // Outputs         wire divideby2;         wire divideby4;         wire divideby8;         wire divi...

User-defined functions Functions that we define ourselves to do certain specific task are referred as user-defined functions. Functions that readily come with Python are called built-in functions. If we use functions written by others in the form of library, it can be termed as library functions. All the other functions that we write on our own fall under user-defined functions. So, our user-defined function could be a library function to someone else. Advantages of user-defined functions 1. User-defined functions help to decompose a large program into small segments which makes program easy to understand, maintain and debug. 2. If repeated code occurs in a program. Function can be used to include those codes and execute when needed by calling that function. 3. Programmers working on large project can divide the workload by making different functions. Example 22: Write a python script to print a message using user-defined function. def message( ): print("Iam working...

HONOR X60 :  Honor X60   is available in  four Variants: 8GB+128GB ,8GB+256GB , 12GB+ 256GB  ,12GB+512GB and three Colors options Elegant Black ,Haihuqing and Moon Shadow White  Honor X60 Pro Is available in four Variants: 8GB+128GB | 8GB+256GB | 12GB+ 256GB , 12GB+512GB and Only 12GB+512GB supports China Mobile Beidou satellite SMS communication. X60 pro has four Color variants Basalt Gray ,Burning Orange , Sky Blue and Elegant Black image credits: Honor China #Honor #HonorX60series #HonorX60 #HonorX60Pro

Realme P1 Speed 5G key specifications  It features a 120Hz refresh rate OLED(oraganic light emitting diode)display. Realme p1 speed is powdered by Dimensity 7300 Energy chip. equipped with  LPDDR4x RAM 26GB RAM (including virtual RAM) ,256GB UFS 3.1 storage -it is packed with 5,000mAh battery supports 45W charging. It has  6050mm2 stainless steel VC(vapour chamber)cooling.  It features a 90fps gaming with GT mode Other info  Dual speakers ,Wi-Fi 6,Bluetooth 5.4 IP65 rating, 7.6mm thickness  Image credits : Flipkart  #Realme #RealmeP1Speed #RealmeP1Speed5G #qyestverse #qyest